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STE12PS
12 channel integrated PSE line manager
Preliminary Data
Features

PSE power control device Supports up to 12 independent or four 30W, "boosted" ports Wide operating range: up to 90V IEEE 802.3af compliant Open circuit detection: AC and DC methods Advanced power management algorithm Current sensing with as low as 500m, external, series resistors No need for external FETs In-rush current control Short-circuit protection Adaptable signature detection capability On-chip 3.3V SMPS controller Low-noise, 12-bit ADC Standard I2C interface Parallel monitor interface The STE12PS is fully programmable, supporting the detection and powering of IEEE802.3af as well as legacy PDs. The flexibility of the STE12PS allows the user to select a suitable system configuration: up to 12 ports as well as 4 "boosted" channels. If needed, the STE12PS can also efficiently manage cases or applications where a limited amount of power is available to the ports (smart-power capability) by means of integrated, power MOSFET devices. All operations are controlled via the I2C bus also notifying externally some ports status condition via dedicated pins. Ethernet port isolation can be easily maintained thanks to an integrated 3.3V SMPS power source and by means of optocouplers. The STE12PS has five address selection inputs to choose up to 32 possible different addresses. Power can be provided to the PD using either spare lines of the Ethernet cable or using the data wires, as specified by IEEE 802.3af.
PBGA23x23
Description
STE12PS is designed to supply power over multiple Ethernet channels in order to avoid different, individual power supply units for applications such as Web cams, IP Phones, Bluetooth access points and WLAN access points. The equipment that provides the power to the twisted pair cabling is referred to as Power Sourcing Equipment (PSE). The PSE's main functions are: looking for links to a Powered Device (PD), classifying a PD, supplying power to the link, monitoring power on the link, and removing power from the link.
November 2006
Rev 1
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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Contents
STE12PS
Contents
1 2 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 3.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Detection and classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.1 3.2.2 3.2.3 Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Detection and classification FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Power ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1 3.3.2 3.3.3 Under load (disconnection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Short circuit, overload and overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . 15 Thermal monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 3.5 3.6 3.7 3.8 3.9
Internal 3.3V/10V generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Logic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6MHz clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Smart-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power boost mode - 30W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Measurement and parameter codings . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4 5
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I2C slave protocol overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 5.2 5.3 5.4 5.5 5.6 5.7 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Error cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I2C device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Register addressing: write command format . . . . . . . . . . . . . . . . . . . . . . 28 Register addressing: read command format . . . . . . . . . . . . . . . . . . . . . . 29 Parallel monitoring interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6
Electrical specifications and timings . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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STE12PS
Contents
7 8 9 10
Ball coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Package information - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . 41 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Block diagram
STE12PS
1
Figure 1.
Block diagram
STE12PS functional block diagram
Analog front end
I2C interface Smart power & port priority management Power-on control inrush current limiting Programmable detection/ classification 12-bit ADC Line detection classification monitoring AC disconnect ~ generator & 50Hz detector 12 x power switches 3.3V SMPS controller Internal clock generator
PC00101
Programmable timer settings Monitoring output interface
Digital controller
Tri-level temperature protection
Figure 2.
Typical application diagram
+48V Low Cost PMOS L1 D3 C1 D4 R3 C2 3.3V To Other Devices D1 x 12
R1 R2
SMPS_VL VL GNDs
RLIM VDRIVE
SMPS_GND
V3_3 Px FSRPx D2 x 12
To Opto Couplers
I2C BUS
I2C_ADDRx SCLIN SDAIN SDAOUT INTN
STE12PS
SSRPx
Rsense x 12
HQGND Rmon RMONS SPx RMONF
CLKgenx
ACSx
C4
C5
C3 x12
PC00102
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STE12PS
Pin description
2
Table 1.
Pin description
Analog pins description
I/O O O O O O O O O O IO O O I I Function Anti-aliasing filter capacitor to be connected between the analog input and ground to improve ADC noise performance. C = 180pF. Anti-aliasing filter capacitor to be connected between the analog input and ground. C = 180pF. Anti-aliasing filter capacitor to be connected between the analog input and ground. C = 100nF. Anti-aliasing filter capacitor to be connected between the analog input and ground. C = 100nF. Anti-aliasing filter capacitor to be connected between the analog input and ground. C = 180pF. Detection rise/fall time capacitor (up to 25nF). Tr/f can be set from 1ns to 4ms. SMPS precision, external, current limiting reference resistor: 100m External p-channel MOSFET gate driving voltage for SMPS. It provides a square wave with VL as upper limit and (VL-10V) as lower limit voltage. Switched Mode Power Supply (SMPS) soft start capacitor, 200nF. SMPS feedback pin, Cfb = 2.2nF Power DMOS device drain, if DMOS is turned-on, channel "n" where n = 1,...12 is activated. It provides a 50Hz AC disconnection signal for port "n", n = 1, ... 12. Detection classification and AC disconnection sensing port "n", n = 1, ... 12. Line current to the monitoring resistor for channel "n", n = 1,... 12. Allowed values are 0.523, 1.05, 1.58 and 2.1ohms (see also SENSPROG preset pins). Sensing pin. Source terminal for power DMOS connected to the sense resistor for channel "n", n = 1,... 12, a "forcing" pin. Mirror monitoring resistance (500 x Rsense) pin to let internal ADC evaluate line currents. Forcing pin. Mirror monitoring resistance (500 x Rsense) pin to let internal ADC evaluate line currents. A "sensing" pin. Reference bias resistor: 18.7k Crystal oscillator pin1 for high performance clock generation. Crystal oscillator pin2 for high performance clock generation. Master clock output for multi device configuration. Low profile clock input pin or clock input pin in multi-device configuration. 50Hz sinusoidal input 50Hz sinusoidal output, internally generated
Pin name IDET_HVLV IMON_HVLV Vbat_mon Vbatref I_REF CDETSLOW RSENSE VDRIVE SFTSTR FB Pn ACSn SPn SSRPn
FSRPn RMONF RMONS RREF CLK_GEN1 CLK_GEN2 MCLK CLK_GEN3 ACin ACout
O O O I I I O I I O
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Pin description
STE12PS
Table 2.
Digital pins description
I/O Function
Pin name Reset RESETN Status flag interface
I
Reset pin. Active LOW
CH_SELn
O
Channel identification "n", where n = 1,... 12. Indicates the channel whose status flags (POK, ...) are currently notified externally. CH_SEL is incremented every 60 * MCLK clock cycles. The status flag notification is enabled via the configuration register Global_cfg2, STATUS_FLAG_EN bit. Power OK flag. This flag indicates condition of the currently powered channel: `1'power ON and NO faults are present `0'power OFF or (power ON and faults present) Overload Alarm Flag for the currently powered channel. Current overload condition (Icut is over threshold): `1'channel overload condition detected `0'NO overload Short circuit Alarm Flag for the currently powered channel. Current limiting condition: `1'Overcurrent or detection failed condition detected `0'ANY Short Circuit condition detected AC/DC Disconnection Alarm Flag for the currently powered channel: `1'AC/DC disconnection detected `0'ANY disconnection detected Detection/Classification flag. `1'Detection or Classification procedure is running `0'Detection/Classification procedure is not running. `1' VL, 10V and 3.3V supply Power ON succeeded
POK
O
OVLD
O
OVCUR
O
AC_DC_DISCON
O
DET_CLASS Por_N Thermal monitoring
O O
T_MONITORx
O
Thermal monitoring (x = 0,1). These bits encode the internal temperature's threshold measured in the following way: "00" Temperature under 110 C "01" Temperature between the 110 C to 130 C "11" Temperature between the 130 C to 150 C "10" Temperature is above 150 C
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STE12PS
Pin description
Table 2.
Digital pins description (continued)
I/O Function
Pin name Configuration signals A_BN_SEL
I
A or B alternative configuration mode select. `0'Alternative B (Midspan-PSE) `1'Alternative A (Endpoint-PSE) 12- or 4-boost channel select. x = 0,1. `00' 12 channels configuration `01' NA `10' NA `11' 4-boost channel configuration AUTO Start Mode enable. `0'Auto Start Mode disabled: all the ports are disabled after Reset, Neither detection nor power on is performed (MODE[1:0] register selected to Power Down at the reset event) `1'Auto Start Mode enabled: all the ports are automatically enabled, detection, classification and power are performed (MODE[1:0] register selected to AUTO after the reset event) SMPS (Switch Mode Power Supply) mode selector bit (supplier / User). When Not connected the device works as DC-DC converter controller. Preset pins for sensing resistor programmability (x=0,1). The programmed value must match the mounted Rsense resistors. `00' Rsense = 0.5 `01' Rsense = 1 `10' Rsense = 1.5 `11' Rsense = 2
CH_NUMx
I
AUTO_START
I
S/UPIN
I
SENSEPROGx
I
Power ON controller signals POWER_ENx I2C Signals I I I O O This defines the device address for the I2C interface. x = 0, ... 4. Serial clock input pin for the I2C interface. Serial data input pin for the I2C interface. When "jumpered" with the SDAOUT pin, this connection becomes the standard bi-directional serial data line (SDA). Serial data output pin for the I2C interface. When jumpered with the SDAIN pin, this connection becomes the standard bi-directional serial data line (SDA). I2C Open drain output that goes low when interrupt event is notified I Reserved. (x = 0, ...11).
I2C_ADDRx SCLIN SDAIN SDAOUT INTN Test mode signals
TEST_MODEx
I
Test Mode Enable (x = 0,1). `00' Functional mode `01' Reserved `10' Reserved `11' Reserved Reserved. Preset to `0'.
SCAN_EN
I
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Pin description
STE12PS
Table 3.
Power and ground pins description
I/O I I I I I/O I I I Analog grounds SMPS power ground +48V battery voltage for SMPS 3.3V supply 10V supply to power-up the output DMOS and minimize its ON resistance Dedicated ground for Kelvin line current sense resistor (a high quality ground) Digital grounds +48V battery voltage. Function
Pin name GND, AGND SMPSGND SMPS_VL V3_3,Vdd,Vdde V10, Vdd10 HQGND DGND, gnd, gnde VL
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STE12PS
Functional description
3
Functional description
The STE12PS architecture provides a complete PSE interface and smart digital controller to efficiently manage the functions in a PoE system. All operations can be controlled through R/W registers via a standard I2C bus interface. The STE12PS is designed to control power delivery of up to 12 separate lines. This is performed by controlling 12 integrated, power MOS transistors connected to the low side of the line - monitoring the line voltage and sensing line current by means of external, series sensing resistors (one per port). Turning on a port means to switch the relative MOS transistor thus controlling the inrush current in order to rise the port voltage up to 48V (typical battery voltage) after a valid PD signature has been detected. The flexibility of the STE12PS allows the user to select a suitable system configuration: 12 "standard" 15W or 4 "boosted" 30W channels, by means of pins CH_NUMn. Also, one can select the type of architecture (Endpoint PSE/ Alternative A or Midspan PSE/Alternative B) for all channels via pin A_BN_SEL. Some typical applications for the STE12PS include:

Ethernet switches/routers Midspan power supplies
IP-PBX WLAN access points
3.1
Operating modes
The digital controller can operate in one of five possible modes for all the channels, selectable through the Global Configuration registers: Stand-by, Auto, Semi Auto, Manual or Power Down. When the reset condition is removed, the controller defaults to Power Down mode if the AUTO_START pin is tied low; if AUTO_START is tied HIGH the mode is configured in AUTO. The mode can be changed only during a limited amount of time (100ms), after the reset is released, accessing the Global Configuration registers before the detection procedure is started, or placing the device in STAND-BY mode via the I2C interface. The characteristics of the Five possible operating modes are described below:

STAND-BY: the controller allows only the read write operations suitable for changing programmability. To enable this mode set the reset bit 1 of the REG0x05. AUTO: the controller autonomously performs detection, classification and Power ON command without the need of host commands. A subset of status flags stored in the channels monitor registers is reported externally through the Status Flag Notifies pins allowing operation without the presence of the host controller. SEMIAUTO: after a triggering command the controller autonomously performs detection and classification waiting a dedicated command from host processor for the power on. Based on the detection and classification results reported in the Channels Status registers, the host controller can decide to power on the selected channel. The disconnection of a channel is automatic as in the AUTO mode, unless disabled. MANUAL: any action is performed manually. The host controller has the responsibility to force any state transition in the FSM. Then based on the measures performed automatically by the ADC on several parameters, the host controller can decide to
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Functional description
STE12PS
classify the channel and afterwards to issue the power on command. The STE12PS controller can also automatically disconnect a channel in fault condition (if not enabled, the STE12PS will notify automatically only a short circuit condition or an AC disconnection event. Overload or DC disconnection is responsibility of the host controller.) The host controller can also power on a channel skipping detection and/or classification procedures.
POWER DOWN: the controller is put in power down state. No actions are performed until the power down mode is removed.
For all operating modes, except power-down and stand-by, the power ON/OFF condition of each channel can also be managed, directly, by the host processor or controller via a dedicated command. Moreover, the power removal procedure is performed automatically (also in MANUAL mode) when a fault event has been detected (AC/DC disconnection, overload or overcurrent); this behavior can be changed configuring appropriately some dedicated enable/disable bits of channels event registers. With Priority Management in AUTO mode and Smart-power management enabled, it is also possible to set different priorities for different channels. The STE12PS will probe channels starting from those with the highest priority. In case of a shortage of available power, it is also possible to disable powering of newly detected, lower priority ports until the highest detected ones are served.
3.2
3.2.1
Detection and classification
Detection
The STE12PS looks for, in turn on the free available ports (according to the priority list if enabled), for a valid PD signature (25k slope characteristic) by driving two different voltage levels at the port (4V and 8V), and calculating the slope resistance/ conductance by monitoring the current difference. The equivalent circuit for the IEEE802.3af detection phase is shown in Figure 3 below.
Figure 3.
IEEE802.3af detection circuit
Zsource D2 P+ D1(one per port) is external. D2 (one per port) external is required only if the AC_Disconnection function is used, otherwise it is internally emulated.
D1
+
V
_
P-
PC00103
As detection is performed by multiplexing a common voltage generator. If more than one port is connected to several PDs, an extra delay in the detection start will be introduced. See Table 10: Electrical characteristics, parameter Tdetd.
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STE12PS
Functional description
By default, the STE12PS will recognize a valid signature with the following characteristics: - - an inverse slope of the port current vs. voltage (I-V) characteristic measuring between 19 and 26.5k (Rdl and Rdh), a port capacitance of less than 4F.
If required, the STE12PS can also perform a custom, resistive detection search - modifying the acceptance window. This can be easily performed by changing the Rdh and Rdl limits or by changing Gdl and Gdh via the logic interface. In Midspan applications, where power is applied via spare wires, when the PSE fails to detect a PD, the port remains in high-impedance (Hi-Z) for at least two seconds. If the signature resistance is greater than 500k, then the two second wait is avoided. Transition rates of the port voltage between the two probing levels can be adjusted with capacitance Cdetslow. Table 4.
Class 0 1 2 3 4 0
PD power classification
Usage Default Optional Optional Optional Optional Default Maximum power level at PSE output (Pall) 15.4W (programmable) 4W (programmable) 7W (programmable) 15.4W (programmable) 15.4W (programmable) Power level at PD input 0.44 to 12.95W 0.44 to 3.84W 3.84 to 6.49W 6.49 to 12.95W Reserved 0.44 to 12.95W Iclass Iclass < Ithcl0 Ithcl0 < Iclass < Ithcl1 Ithcl1< Iclass < Ithcl2 Ithcl2 < Iclass < Ithcl3 Ithcl3 < Iclass < Ithcl4 Ithcl4 < Iclass
3.2.2
Classification
Once a valid signature is detected, the port is probed for classification in order to perform smart-power management (if enabled). Port probing is performed by forcing a DC voltage in the range of 16V to 18V (one DC generator multiplexed between the channels) and monitoring current Iclass. The measurement is repeated and stored in the Channel Monitor Classification registers to ensure a coherent classification. The PD power class is defined as shown in Table 4 above. The detected class is then stored in the Channel Status registers.
Note:
The power absorbed in a link is calculated considering the actual value of the battery voltage in order to arrive at a true power measurement result.
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Functional description
STE12PS
3.2.3
Detection and classification FSM
This FSM manages all operations related to the detection and classification procedures. For these two procedures, the following assumptions are made: 1. A channel is detected ONLY if: the channel has not yet been detected, and Channel Detection has been enabled, and b) the Backoff Detection timer and Subsequent Attempt timer are NOT running (after a corresponding fault detection or failed signature). A channel is classified ONLY if: a) Channel Classification is enabled, and b) the previous related detection procedure has reported an Rgood/Ggood value (Auto and SemiAuto modes). a) STARTUP: the following operations are related to the startup procedure: - - RESET: reset and initialize all digital aspects of the STE12PS, WAIT_POWER_UP: wait 100ms for completion of the power-up procedure. During this period, the I2C bus is active - allowing the host to initialize registers while the detection procedure is waiting to start. DETECTION START: all setting-up needed to start operations is performed in this state. The first battery voltage sample is latched in a dedicated register.
2.
Three general macro operations can be performed:
-
DETECTION: the following operations are related to the detection procedure for the channel selected: - - - - Low Voltage detection command (4V) is issued via registers; detection timer is started to execute the command for a duration of 1/2Tdet ms. Wait for 5ms to acquire a stable measurement. Sampled sensing current values are acquired via A/D converter. The samples previously acquired are averaged and the resulting value, reported into the Channels Monitor register, is compared against programmed min/max values. If the sensing current is higher than maximum allowed value, the detection procedure is considered as having FAILED: backoff timer is started (Alternative B) and an alarm flag raised according to the Channel Status registers. If the sensing current results lower than the minimum allowed value the detection procedure is continued: the alarm flag is raised in the Channel Status registers. The described operations are repeated for the High-Voltage detection command (8V). Signature Resistance is calculated: If 2sec < Gmeas < Glow or Ghigh < Gmeas, then backoff timer is started (Alternative B) and detection result failure is reported in the Channel Status registers. Else, Glow < Gmeas < Ghigh and the result of a successful detection is reported in the Channel Status registers.
- - - -
-
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STE12PS
Functional description
CLASSIFICATION: The following operations are related to the classification procedure for the corresponding channel - - - - - If classification is not enabled, the default Class 0 is assigned. High Voltage detection command (17V) is issued via registers; detection timer is started to execute the command for 15ms duration. Wait for 5ms to acquire a stable measurement Sampled sensing current values are acquired via A/D converter. Average the previously acquired samples and report the resulting value in a dedicated register. The power class is identified and the result is reported in the Channel Status registers. Channel is ready to be powered: if the smart-power algorithm is enabled (via the MISCELLANEOUS registers) the channel is powered only if the required power is within the remaining power budget; the channel can be powered regardless of the power-check availability via registers.
-
If the power availability check has a positive result (or it hasn't been performed), the channel is powered. Otherwise, it is rejected, and the alarm flag raised in the Channel Events register. The channel number is registered into a scheduler FIFO so that power will again be available when the channel is ready to be switched-on. Figure 4. Detection and classification equivalent architecture
+48V VL Detection/classification + + + +4V +8V 8V +17V
D1 x12 + SPx
Px D2 x12 Digital controller
STE12PS
PC00104
12-bit A/D converter
IDET_HVLV
180pF
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Functional description
STE12PS
3.3
Power ON
After the classification phase the port will be powered. Once activated, the power-on sequencer manages the channel's activation requests received through the signature detection circuitry. For the incoming channel, activation requests are stored in the power-on sequencer and then serviced, one at a time, only when the previously activated channel leaves the current limiting condition that normally occurs during power on due to the capacitive part of the load. (see also smart-power mode and special issues) A port is turned-on by ramping-up the voltage and increasing the current limit to its upper limit. After a programmable time (Tinrush), if the port has reached full voltage and is out of current limitation, it is marked as powered. The related port power bit and the power class bits are set according to the class in the logic interface bit stream. The active ports are continuously monitored in order to detect a fault condition such as Short Circuit, Disconnection or Excess Power (overload).
3.3.1
Under load (disconnection)
Detection of a disconnection, if enabled (default condition), can be performed via a DC and/or AC method - default is DC AC (logical OR):
DC method If this method is selected via the logic interface and if the port current drops under 7.5mA for more than 10ms, then the STE12PS will detect a DC disconnection. If this condition persist for Tmpdo (Table 10), then power is removed and the port is marked as free, enabling a new detection.
AC method If this method is selected via the logic interface, the STE12PS probes the channels via coupling capacitors and detects when the AC load impedance, Zac, exceeds the maximum, 100k limit for a time longer than 20ms. In this case, the PSE will detect an AC disconnection. If this condition persist for a time Tmpdo (Table 10), power is removed and the port is marked as free, enabling a new detection.
Disconnection modes are as following: Disabled, DC method only, AC method only, both AC and DC (combined in OR logic or in AND logic).
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STE12PS
Functional description
Figure 5.
Power ON and monitoring
+48V VL x12 Power DMOS Px x12 Power EN Short Flag 12-bit A/D converter + Digital controller Power On ctrl Power On ctrl Inrush current Inrushcurrent limiting limiting D2 x12 FSRPx D1 x12
SSRPx Rsense x12 (0.5, 1, 1.5, 2 )
HQGND
RMONS
Rmon ( 500xRsense)
RMONF AC disconnect detector 50Hz ~ 5Vpp STE12PS AC_Discon flag
PC00105
ACSx
300nF
SPx
3.3.2
Short circuit, overload and overcurrent
A short circuit is defined when port current reaches 425mA, typ. Moreover, if port voltage drops below 25V, then maximum loop current is decreased, linearly, to limit power dissipation. A short condition is considered as a fault after a period of 65ms, typ. (see Table 10: Electrical characteristics, parameter Tshort). When the above conditions are met, the port is disconnected, and the fault bit set HIGH in the Channel Event registers. Overload or excess power is defined when port power consumption reaches 15.4W for longer than 65ms, typ. (see Table 10: Electrical characteristics, parameter Tovld). If smart-power management is active, then the overload power limit is set instead according to the power class. When the above conditions are met, the port is disconnected, and the fault bit is set HIGH.
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Functional description
STE12PS
Monitor overload FSM
This FSM manages all operations related to monitoring an overload event.
All operations described below are related to channels currently powered.

STARTUP: the following operations are related to a startup procedure: - START: channel to be monitored is selected. POWER MEASUREMENT: the following operations are related to a power measurement procedure - - - - SAMPLE Imeas: the current measurement is sampled and the next powered channel is prepared for the next monitor procedure. MEASURE Power: the power is measured and its value is compared against the required Power class. START MONITOR OVERLOAD: if the measured power exceeds the required power class the Tovld timer and the averaging process are started. COUNTER RESET: Tovld timer is reset if the measured power doesn't exceed the required
POWER REMOVAL: the following operations are related to a power removal procedure: - - COUNTER CHECK: all Tovld timers are checked, and those that have expired are identified. POWER REMOVAL: all the channels whose timers have expired and whose average power exceeds the maximum are switched OFF through the POWER_EN(n) pins. ALARM SET: for all the channels whose timers have expired, a corresponding alarm flag is raised in the Channel Event registers, and the related Ted timer is started.
-
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STE12PS
Functional description
Monitor overcurrent FSM
This particular FSM manages all operations related to procedures that are able to monitor an overcurrent event.
All operations described below are related to channels currently powered.

STARTUP: - - - - - START: the channel to be monitored is selected. SAMPLE Vbat: every 12 channels cycle the Vbat measurement is executed. Imeas CHECK: if Imeas>Ilim the I_LIM_FLAG is raised and the next powered channel is prepared for the next monitor procedure. START MONITOR: the Tlim counter is started if I_LIM_FLAG is found asserted. COUNTER RESET: if I_LIM_FLAG is found de-asserted Tlim counter is reset taking into account that glitches of duration less than 10ms are filtered. COUNTER CHECK: all the Tlim timers are checked and those expired are identified. POWER REMOVAL: all the channels whose timer is expired are switched OFF. ALARM SET: for all the channels whose timers are expired a corresponding alarm flag is raised in the FAULT_EVENT_CHn register and the related Ted timer is started. VOLTAGE BATTERY: OVERCURRENT CHECK: the following operations are related to an overcurrent check
POWER REMOVAL: the following operations are related to a power removal operation: - - -
3.3.3
Thermal monitoring
The procedures performed by the digital controller are impacted by the thermal monitoring data indicating the measured temperature. Its behavior is based on a three-level control system: 1. When the chip's internal temperature reaches 110C, only the channels already powered will be serviced. Possible new ones, will be rejected, redetected and eventually processed when the internal temperature cools down to 100C. This behavior can be disabled setting the proper bit register. A second temperature threshold is set at 130C. When this value is reached, the channels that are in current limiting or inrush condition are immediately switched OFF, and their reactivation, subject to positive redetection, will only be possible when the chip's internal temperature has cooled down to 100C. This behavior can be disabled by setting the proper bit register. The third temperature threshold is set at 150C. When this temperature is reached, all activated channels will be immediately switched OFF, and their reactivation, subject to positive redetection, will only be possible when the chip's internal temperature has decreased to 100C. This behavior cannot be disabled.
2.
3.
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Functional description
STE12PS
3.4
Internal 3.3V/10V generator
The STE12PS can be configured either as 3.3V and 10V generator or load by means of the S/U control input. In this manner, the need for extra, low-voltage batteries is avoided, greatly simplifying the system design. If S/U is left open, the device will operate as an SMPS controller. With the SMPS configured at 3.3V, the device can be used to power up a "1Amp" load with high efficiency voltage conversion.
Figure 6 on page 19 shows a typical DC-DC, buck converter configuration for the 3.3V supply. The 10V supply is generated by means of an internal, linear regulator. The 3.3V supply can source up to 1A.
In Figure 7, use of a small transformer for the 10V supply can save up to 0.3W for each powered device. Both the 3.3V and 10V supplies can power others devices.
Figure 8 depicts a typical application with an external supply.
3.5
Logic interface
The STE12PS can operate autonomously - notifying, externally, ports status via dedicated pins (Parallel Monitor Interface) - or it can be controlled as a slave device via the I2C interface by a host processor. In the latter case, the host can perform system configurations, monitor status conditions and assert alarm flags making it possible to drive, manually, different operations for detection, classification and monitoring.
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STE12PS
Functional description
Figure 6.
Simple SMPS
+48V To other devices
Ext low cost PMOS
VL SMPS
RLIM
VDRIVE
V3.3
V10 Internal linear regulator
FB
PMOS driver E/A
Current limiting
PWM & ramp generator
Soft start SFTSTR Clock gen
RREF1 Bandgap & reference
STE12PS
S/Upin
PC00106
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Functional description
STE12PS
Figure 7.
Advanced SMPS
+48V
.
VL SMPS RLIM VDRIVE
E/A
To other devices
V3.3
V10 FB
PMOS driver
Current limiting
PWM & ramp generator Soft Start
RREF1 Clock gen Bandgap & reference
SFTSTR
STE12PS
S/Upin
PC00107
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STE12PS
Functional description
Figure 8.
+48V +3.3V
With external power supplies
+10V Optional VL RLIM VDRIVE V3.3 V10 FB
PMOS driver E/A
VL SMPS Current limiting PWM & ramp generator Soft start SFTSTR Clock gen.
RREF1 Bandgap & reference
STE12PS
S/Upin
PC00108
3.6
6MHz clock generator
Figure 10 on page 23, and Figure 11 and Figure 12 on page 24 show the three possible clock generation configurations: a) with a 6MHz crystal for a high precision clock, b) with an external RC for low-cost applications, c) with an external clock.
3.7
Smart-power mode
When this mode is enabled, the whole system is set to manage and deliver a limited amount of power to the channel. In Auto Mode, it is actually possible to set a maximum power budget for the device. When a PD is connected to a port, the STE12PS verifies the class and decides to power the line only if there's enough power available. It is also possible to set different priorities for the different channels. The device probes channels starting with those of highest priority. In case of shortage of available power, it is possible to disable the powering of newly detected ports of lower priority until the ones with a higher detected priority are serviced. If a channel exceeds its power class, that channel can be powereddown, and its power made available again. A 12-bit ADC is used to provide high-quality voltage and current measurements during the various phases of port detection,
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Functional description
STE12PS
classification and powering. These measurements can be loaded into dedicated registers via the I2C bus and are intended to be averaged over time in order to maximize PSSR and noise rejection as well as minimize 50 to 60Hz interference.
3.8
Power boost mode - 30W
When this mode is activated, the device will run the classification extending the IEEE classes with an extra PD_Class boost as detailed in Table 4. If class boost is detected, an equivalent double port (parallel of two channels) is switched-on allowing up to 30W of power to be supplied. All the other IEEE classes behave as a standard port (powering on one channel only). Table 5 below describes channel parallelism: Table 5. Power boost mode: master/slave channel parallelism
Master Channel (MC) 1 2 3 4 Slave Channel (SC) 5 6 7 8
Channels in boost mode behave as master or slave according to the above table. Detection and classification are performed only on the master ports. If a class 0 to 4 PD is detected, only MC is powered. Otherwise, if Boost Class is detected, both MC and the related SC are powered. Once powered, any fault condition (short circuit, over current, over power, PD disconnection) occurring either for MC or SC forces the reaction of both channels. All status and measurement information are stored in registers pertaining to the MC. Detection procedure is the same as the standard one while the classification phase is performed with 3 classification impulses (total classification time 70ms).
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STE12PS
Functional description
Figure 9.
+48V
Power boost mode
VL
Det/Class
X8 Power EN Short Flag 12-bit A/D converter + Power-on ctrl, Inrush current limiting
X4 Power DMOS
MC
D1 x12
D2 x4
SC
SSRPMC SSRPSC Rsense Rmon ( 500xRsense)
Digital controller
HQGND RMONS RMONF
AC disconnect detector
ACSMC SPMC
300nF
~
STE12PS
AC_Discon flag
PC00109
Figure 10. Crystal oscillator
STE12PS
MCLKout
CLKgen3
CLKgen2 16pF
CLKgen1 16pF
6MHz Crystal
PC00110
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Functional description
STE12PS
Figure 11. Low cost RC oscillator
STE12PS
MCLKout
CLKgen3 820 ohm
CLKgen2
CLKgen1
210pF
PC00111
Figure 12. With external oscillator
STE12PS
MCLKout
CLKgen3
CLKgen2
CLKgen1
External 6MHz
PC00112
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STE12PS
Functional description
3.9
Measurement and parameter codings
Table 6 below lists codifications for the various parameters such as detection conductance or resistances, classification or monitoring currents, port voltages, port powers and power budgets.
Table 6.
Measurement and parameter codings
Description Detection current Detection conductances Detection residences Current classification Channel current during powering Battery voltage Channel power usage Range 0 to 1023 0 to 256 8 to 48.96 0 to 70 0 to 1024 0 to 70 0 to 35000 Step 1 0.250 0.01 0.065064 0.0312662 0.27451 35.149 Units A S K mA mA V mW Number of steps 1024 1024 4096 1024 32768 256 1024
Parameter Idet Gdet, Gdl, Gdh Rdet, Rdl, Rdh(1) Iclass Imon Vport Pmeas
1. Rdet, Rdl and Rdh are the alternative to Gdet, Gdl and Gdh which are the default. If Rdet measures more than 500kohms, the "open-circuit" flag is raised, that is set HIGH.
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I2C interface
STE12PS
4
I2C interface
The STE12PS has an I2C interface to allow the access to the internal device registers. The external controller can be fully isolated from the Ethernet port thanks to an integrated 3.3V SMPS power source and using optocouplers on I2C bus.(Figure 13).
Figure 13. Isolated ethernet power system using optocouplers for I2C interface
Controller GND SDA bus SCL bus INT bus
OPC 1 SDAIN SDAOUT DGND SCLIN INTn OPC 2 Controller VDD
OPC 3
STE12PS
OPC 4 Digital ground 3.3V
PC00113
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I2C slave protocol overview
5
I2C slave protocol overview
The interface is capable of recognizing its own address (7 bit). Data and addresses are transferred as 8-bit bytes, MSB first. The first byte following the start condition contains the device address. A 9th clock pulse follows the 8 clock cycles of a byte transfer during which the receiver must pull LOW the SDA line to acknowledge the transfer. The speed of the I2C interface is fixed at Fast I2C, that is, 100 to 400kHz.
5.1
Functional description
As soon as a start condition is detected, the address is received from the SDA line and sent to a shift register; then it is compared with the internal address that is composed by the five pins for the five LSB and by a hardwired value equal to "01" for the other two bits.
In case of address mismatch the interface ignores it and waits for another Start condition. If address is matched the interface generates an acknowledge pulse.
Following the address reception, POE digital controller receives bytes from the SDA line into the data register via an internal shift register or sends bytes from the data register to the SDA line through the internal shift register. After each byte reception an acknowledge pulse is generated by the controller. A Stop condition generated by the host processor, after the last data byte is transferred, closes the communication.
5.2
Error cases
An error state is generated when Stop or Start conditions are detected during a byte transfer. If it is a Stop then the interface discards the data, releases the lines and waits for another Start condition. If it is a Start then the interface discards the data and waits for the next slave address on the bus.
5.3
Interrupts
Irq register bits indicate which signals can generate an interrupt. The register is read only and to clear the interrupt bits the corresponding source event has to be cleared. The logic OR condition of the interrupt bits causes the INTN pin assertion. The INTN assertion can be masked via the interrupt mask register Irq_mask.
5.4
I2C device address
The device is required to have an I2C address of: 01xxxxxb(A6 down to A0). Pins I2C_ADDR[4:0] can be used to set the lower I2C address bits.
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I2C slave protocol overview
STE12PS
5.5
Register addressing: write command format
I2C write command format is shown in Figure 14.
Figure 14. Write command
R/W ACK
S
Device address
Register address (K)
6
5
4
3
2
1
0W.
7
6
5
4
3
2
1
0
ACK
Write data
Write data (K + 1)
76
5
4
3
2
1
0
.
7
6
5
4
3
2
1
0
ACK
...
Write data (K + N)
76
5
4
3
2
1
0
The formatting bits shown in Figure 14 are defined as follows:

S - I2C start condition P - I2C stop condition ACK - acknowledge NACK - not acknowledge R/W - read/write
The device address is the value specified in I2C device address. The register address is an eight-bit value that is written into an internal Index Register. Each time a byte of data is written to, or read from the POE controller, the Index Register increments by one. If the initial value written to the Index Register is K, then the byte immediately following the Register Address byte is written to the register with an address of K. The next byte is written to the register with the address of K+1, and so on. An I2C write command can contain from 0 to 255 write data bytes. Write commands to an unknown register location are ignored by the interface. As shown in Figure 14, bits are ordered with the most significant bit first.
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P
ACK
ACK
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STE12PS
I2C slave protocol overview
5.6
Register addressing: read command format
The general format of the read command is shown in Figure 15. First part of the general read command consists of writing an address to the Index Register of the POE controller. If the Index Register already contains the address of the register to be read, as the result of a previous read or write command, then it is not necessary to write that address to the Index Register again. After each byte is read from the POE controller, the Index Register is required to increment by one. A read command can contain from 0 to 255 bytes.
Figure 15. Read command
R/W ACK
ACK 0 0 0
S
Device address
Register address (K)
6
5
4
3
2
1
0W.
7
6
5
4
3
2
1
R/W ACK
S
Device address
Read data (K)
6
5
4
3
2
1
0R
.
7
6
5
4
3
2
1
ACK
Read data (K + 1)
Read data (K + 2)
76
5
4
3
2
1
0
7
6
5
4
3
2
1
ACK
...
Read data (K + N)
P
76
5
4
3
2
1
0
ACK
ACK
P
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I2C slave protocol overview
STE12PS
5.7
Parallel monitoring interface
In order to monitor the status of the different ports without the I2C register addressing, a simple, output status interface has been implemented. This digital interface is comprised of 9 output pins: CH_SEL[3:0], POK, OVLD, OVCUR, AC_DC_DISCON and DET_CLASS. Bits CH_SEL[3:0] indicate the channel status flags (POK,..., DET_CLASS) that are currently notified, externally. CH_SEL is incremented every 60MCLK clock cycles.
POK stands for Power OK. When HIGH, it indicates that the channel is currently powered-on in normal condition. OVLD stands for OverLoad and indicates a faulty condition due to abnormal power dissipation (more than Pclass) of a powered channel. OVCUR stands for OverCurrent, and it highlights a channel whose current has reached the power-on current limit of 425mA (typ. value).
Bit AC_DC_DISCON goes HIGH when a powered channel fails in providing a correct MPS (maintain power signature). This typically happens when a PD is disconnected from the line.
DET_CLASS indicates a situation where a channel is not yet powered and whose "signature" is currently being probed.
Status flag notification is enabled by bit STATUS_FLAG_EN of the configuration register Global_cfg2. By default this bit is HIGH, that is, enabled. This information is particularly useful in simple applications without a microprocessor or for testing purposes. Another use is to easily build-up an LED graphical interface showing runtime status of the various channels.
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STE12PS
Electrical specifications and timings
6
Table 7.
Electrical specifications and timings
Absolute maximum ratings
Symbol Parameter Battery voltage 3.3V power supply 10V power supply Maximum junction temperature Value 90 3.6 12 150 Units V V V C
VL, SMPSVL Vcc3,Vdd,Vdde V10,Vdd10 Tj
Table 8.
Operating range
Symbol Parameter Operating temperature range Battery voltage Ground separation 3.3V when externally supplied 10V when externally supplied 10V current sink (when externally supplied) Battery current sink (when 10V is externally supplied) Battery current sink (when 10V is self generated) 3.3V current sink (AUTO mode) Value -20 to +85 44 to 57 -0.3 3 to 3.6 9 to 11 6.7 typ. 0.4 typ. 7.4 typ. 20 typ. Units C V V V V mA mA mA mA
Topt VL, SMPSVL GNDs Vcc3, Vdd, Vdde V10, Vdd10 IV10, IVdd10 IVl IVl Iv3.3
Table 9.
Thermal data
Symbol Parameter Value Units
Rth j-amb
Thermal resistance junction-to-ambient (natural convection)
25
C/W
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Electrical specifications and timings
STE12PS
Table 10.
Symbol Detection Vdl Vdh Tds
Electrical characteristics
Parameter Min. Typ. Max. Units Notes
Detection voltage LOW level Detection voltage HIGH level Transient time between Vdl and Vdh Conductance signature, lower limit (Software programmable) Conductance signature, upper limit (Software programmable) Resistance signature, lower limit (Software programmable) Resistance signature, upper limit (Software programmable) Current limit during detection Detection time Detection delay time (from PD insertion to end of detection phase)
3.7 7.4 300
4 8
4.3 8.6
V V s
Between port terminals Between port terminals Adjustable with external capacitor Cdetslow
Gdl
25
50
mhos Software programmable)
Gdh
41
82
mhos Software programmable Software programmable, to be used as an alternative to Gdh Software programmable, to be used as an alternative to Gdl
Rdl
12
24
k
Rdh Idlim Tdet
20
40 1.1 50
k mA ms
12-port configuration, one channel at a time Maximum delay for 12port configuration Back off time in case of failed PD detection, avoided if Rdet > 500k or Gdet < 2mhos
Tdetd
852
ms
Tdbo
Back-off time (midspan mode)
2
sec.
Ted
Error delay time
750
ms
Classification Vcl Icllim Classification probing voltage Current limit during classification 15.9 55 17 18.1 70 V mA One channel at a time, classification measurement has to be considered as sampled and integrated over this time interval. Between port terminals
Tcl
Classification time
15
ms
Ithcl0 Ithcl1 Ithcl2 Ithcl3
Class0-1 current threshold Class1-2 current threshold Class2-3 current threshold Class3-4 current threshold
5.5 13.5 21.8 31.5
6.5 14.5 23 33
7.5 15.5 24.2 34.5
mA mA mA mA
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STE12PS
Electrical specifications and timings
Table 10.
Symbol Ithcl4 Powering
Electrical characteristics (continued)
Parameter Class4-0 current threshold Min. 45.5 Typ. 46.5 Max. 47.5 Units mA Notes
Pall
Maximum power per channel
15.4
W
See also classification paragraph (doubled in case of Boost configuration) Inrush current soft start Disconnect for t > TPMDO (DC disconnection method) Frequency spread related to clock stability
Iinrush Imin
Output current startup mode Power off current AC disconnection sinusoidal generator AC generator open line voltage AC impedance needed to maintain power
400 5
450 10
mA mA
Acfre Vacd Zac
50 2.5 100
Hz Vpp k
Tmpdo
PD power maintenance request drop out time limit (Software programmable)
300
400
ms
The STE12PS will not remove power if the PD maintenance signal is absent for less than 300ms duration. If an absence of power maintenance signal has been detected, the STE12PS shall remove power within 400ms max(1) After time duration of Tovld the STE12PS will disconnect the power from the port. In fault condition for Tovld, the STE12PS will disconnect the port. (1)
In fault condition for Tshort, the STE12PS will disconnect the port.(1)
Icut
Over load current
Pall/Vport
400
mA
Tovld
Over load time limit (Software programmable) Short-circuit/inrush time limit (Software programmable)
50
65
75
ms
Tshort
50
65
75
ms
Ilim
Output load current under short circuit condition
400
450
mA
Max. value of port current during short circuit condition. Power will be disconnected from the port within Tshort Expired Tinrush if the channel is still in limiting condition it is considered in fault
Tinrush
Rise time of Vport time limit
75
ms
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Electrical specifications and timings
STE12PS
Table 10.
Symbol Toff Ron VsLR V10 int Digital Fclk VIH VIL IIH IIL
Electrical characteristics (continued)
Parameter Turn off time Internal MOSFET resistance in ON mode 3V range in generator mode 10V range internally generated 3 3.3 8.7 Min. Typ. Max. 100 1 3.6 Units ms ohms V V Notes From VPort to 2.8V DC
Clock frequency Input HIGH level voltage Input LOW level voltage Input High current Input LOW current 2
6
MHz V @ VDD = 3.3V @ VDD = 3.3V
0.8 30 10
V A A
1. See also timer programmability
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7
VIEW THROUGH PACKAGE
5 INTN SDAIN SDAOUT CH_NUM1 CH_NUM0 AGND IDET_HVL V I_REF Vbatref AGND RESETN PORn vdde gnde vdd POWER_E POWER_E POWER_E N0 N1 N2 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
STE12PS
1
2
3
4
A
CH_SEL0
CH_SEL1
OVLD
SCL
B
CH_SEL2
CH_SEL3
AC_DC_DI DET_CLAS I2C_ADDR I2C_ADDR I2C_ADDR TEST_MO TEST_MO SCON S 0 1 2 DE1 DE0 AGND AGND Vbatmon AGND vdde vdde gnde vdd gnd
IMON_HVL V
POWER_E POWER_E POWER_E N3 N4 N5
C
vdd10
V10
V3_3
POK
OVCUR
I2C_ADDR I2C_ADDR AUTO_ST A_BN_SEL SCAN_EN 3 4 ART AGND AGND AGND AGND vdde gnde vdd gnd gnd
POWER_E POWER_E POWER_E N6 N7 N8
D
SMPSGND
SFTstr
Acin
Acout
gnd
CLK_GEN1 CLK_GEN2 MCLKout CLK_GEN3
VDDA
gnd
gnd
gnd
gnde
gnde
vdd
vdd
gnd
gnd
POWER_E POWER_E POWER_E N9 N10 N11
E
S/U
NC
RREF
gnd
gnd
CdetSlow
NC
NC
F
NC
NC
FB
gnd
RMONS
RMONF
NC
P8_1-2
G
SenseR
NC
SenseProg Pin0 HQgnd FSRp8_1-2
DGND
NC
P8_3
Ball coordinates
H
Vdrive
NC
SenseProg Pin1 ACS8
DGND
FSRp8_3
NC
SP8
J
SMPSVL
NC
ACS5
GND
gnd
gnd
gnd
gnd
gnd
gnd
SSRp8
ACS4
NC
NC
K
VL
NC
SSRp5
GND
GND
GND
GND
GND
GND
GND
SSRp4
FSRp4_1-2
NC
P4_1-2
L
NC
NC
FSRp5_1-2
GND
GND
GND
GND
GND
GND
GND
GND
FSRp4_3
NC
P4_3
M
P5_1-2
NC
FSRp5_3
GND
GND
GND
GND
GND
GND
GND
GND
ACS12
NC
SP4
N
P5_3
NC
ACS1
GND
GND
GND
GND
GND
GND
GND
GND
SSRp12
NC
NC
Figure 16. Balls top view layout (as viewed through package)
P
SP5
NC
SSRp1
GND
GND
GND
GND
GND
GND
GND
GND
FSRp12_12
NC
P12_1-2
R
NC
NC
FSRp1_1-2
GND
GND
FSRp12_3
NC
P12_3
T
P1_1-2
NC
FSRp1_3
GND
GND
ACS7
NC
SP12
U
P1_3
NC
ACS9
GND
GND
SSRp7
NC
NC
V
SP1
NC
SSRp9
GND
GND
FSRp7_1-2
NC
P7_1-2
W
NC
NC
FSRp9_1-2
GND
SSRp6
GND
GND
SSRp2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SSRp3
FSRp7_3
NC
P7_3
Y
P9_1-2
NC
FSRp9_3
ACS6
FSRp6_1-2 FSRp6_3
ACS2
FSRp2_1-2 FSRp2_3
ACS10
SSRp10
FSRp10_1FSRp11_1FSRp10_3 FSRp11_3 2 2
SSRp11
ACS11
FSRp3_3 FSRp3_1-2
ACS3
NC
SP7
AA
P9_3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Ball coordinates
AB
SP9
NC
P6_1-2
P6_3
SP6
NC
P2_1-2
P2_3
SP2
NC
P10_1-2
P10_3
SP10
NC
SP11
P11_3
P11_1-2
NC
SP3
P3_3
P3_1-2
NC
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Ball coordinates
STE12PS
Table 11.
Column 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2
Pad coordinates
Row A B C D E F G H J K L M N P R T U V W Y AA AB A B C D E F G H J K L M N Pin name CH_SEL0 CH_SEL2 vdd10 SMPSGND S/U NC RSENSE Vdrive SMPSVL VL NC P5_1-2 P5_3 SP5 NC P1_1-2 P1_3 SP1 NC P9_1-2 P9_3 SP9 CH_SEL1 CH_SEL3 V10 SFTstr NC NC NC NC NC NC NC NC NC Column 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 Row P R T U V W Y AA AB A B C D E F G H J K L M N P R T U V W Y AA AB A B C D Pin name NC NC NC NC NC NC NC NC NC OVLD AC_DC_DISCON V3_3 ACin RREF FB SenseProgPin0 SenseProgPin1 ACS5 SSRp5 FSRp5_1-2 FSRp5_3 ACS1 SSRp1 FSRp1_1-2 FSRp1_3 ACS9 SSRp9 FSRp9_1-2 FSRp9_3 NC P6_1-2 SCL DET_CLASS POK ACout
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STE12PS
Ball coordinates
Table 11.
Column 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 7
Pad coordinates (continued)
Row E F G H J K L M N P R T U V W Y AA AB A B C D W Y AA AB A B C D W Y AA AB A Pin name gnd gnd DGND DGND GND GND GND GND GND GND GND GND GND GND GND ACS6 NC P6_3 INTN I2C_ADDR0 OVCUR gnd SSRp6 FSRp6_1-2 NC SP6 SDAIN I2C_ADDR1 I2C_ADDR3 CLK_GEN1 GND FSRp6_3 NC NC SDAOUT Column 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 Row B C D W Y AA AB A B C D W Y AA AB A B C D J K L M N P W Y AA AB A B C D J K Pin name I2C_ADDR2 I2C_ADDR4 CLK_GEN2 GND ACS2 NC P2_1-2 CH_NUM1 TEST_MODE1 A_BN_SEL MCLKout SSRp2 FSRp2_1-2 NC P2_3 CH_NUM0 TEST_MODE0 AUTO_START CLK_GEN3 gnd GND GND GND GND GND GND FSRp2_3 NC SP2 AGND AGND SCAN_EN VDDA gnd GND
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Ball coordinates
STE12PS
Table 11.
Column 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12
Pad coordinates (continued)
Row L M N P W Y AA AB A B C D J K L M N P W Y AA AB A B C D J K L M N P W Y AA Pin name GND GND GND GND GND ACS10 NC NC IDET_HVLV AGND AGND gnd gnd GND GND GND GND GND GND SSRp10 NC P10_1-2 I_REF IMON_HVLV AGND gnd gnd GND GND GND GND GND GND FSRp10_1-2 NC Column 12 13 13 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 14 15 15 15 15 15 15 Row AB A B C D J K L M N P W Y AA AB A B C D J K L M N P W Y AA AB A B C D W Y Pin name P10_3 Vbatref Vbatmon AGND GND GND GND GND GND GND GND GND FSRp10_3 NC SP10 AGND AGND AGND gnde gnd GND GND GND GND GND GND FSRp11_1-2 NC NC RESETN vdde vdde gnde GND FSRp11_3
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Ball coordinates
Table 11.
Column 15 15 16 16 16 16 16 16 16 16 17 17 17 17 17 17 17 17 18 18 18 18 18 18 18 18 19 19 19 19 19 19 19 19 19
Pad coordinates (continued)
Row AA AB A B C D W Y AA AB A B C D W Y AA AB A B C D W Y AA AB A B C D E F G H J Pin name NC SP11 PORn vdde gnde vdd GND SSRp11 NC P11_3 vdde gnde vdd vdd GND ACS11 NC P11_1-2 gnde vdd gnd gnd GND FSRp3_3 NC NC vdd gnd gnd gnd gnd RMONS HQgnd ACS8 SSRp8 Column 19 19 19 19 19 19 19 19 19 19 19 19 19 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 Row K L M N P R T U V W Y AA AB A B C D E F G H J K L M N P R T U V W Y AA AB Pin name SSRp4 GND GND GND GND GND GND GND GND SSRp3 FSRp3_1-2 NC SP3 POWER_EN0 POWER_EN3 POWER_EN6 POWER_EN9 CdetSlow RMONF FSRp8_1-2 FSRp8_3 ACS4 FSRp4_1-2 FSRp4_3 ACS12 SSRp12 FSRp12_1-2 FSRp12_3 ACS7 SSRp7 FSRp7_1-2 FSRp7_3 ACS3 NC P3_3
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Ball coordinates
STE12PS
Table 11.
Column 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 22 22 22 22 22 22 22 22 22 22 22 22 22 22
Pad coordinates (continued)
Row A B C D E F G H J K L M N P R T U V W Y AB A B C D E F G H J K L M N P Pin name POWER_EN1 POWER_EN4 POWER_EN7 POWER_EN10 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC P3_1-2 POWER_EN2 POWER_EN5 POWER_EN8 POWER_EN11 NC P8_1-2 P8_3 SP8 NC P4_1-2 P4_3 SP4 NC P12_1-2 Column 22 22 22 22 22 22 22 22 Row R T U V W Y AA AB Pin name P12_3 SP12 NC P7_1-2 P7_3 SP7 NC NC
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Package information - mechanical data
8
Package information - mechanical data
In order to meet environmental requirements, ST Microelectronics offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST Microelectronics trademark. ECOPACK specifications are available at: www.st.com. Package code: TN JEDEC/EIAJ reference number: JEDEC standard No. 95-1, section 14 (ball grid array package design guide) Table 12.
Ref. Min. A A1 A2 b D D1 E E1 e f ddd 0.950 0.875 22.800 0.450 22.800 0.270 1.320 0.500 23.000 21.000 23.000 21.000 1.000 1.000 1.050 1.125 0.200 0.950 0.875 1.000 1.000 23.200 22.900 23.000 0.550 23.200 0.450 22.900 Typ. 1.720 Max. Min. 1.620 0.350 Typ. 1.720 0.400 1.320 0.500 23.000 0.550 23.100 21.000 23.100 21.000 1.050 1.125 0.200 Max. 1.820 0.450
Package dimensions
Databook (mm) Drawing (mm)
Note:
1 2 3 4 5
Maximum mounted height, dimension A, is 1.77mm based on a 0.35mm ball pad diameter. Solder paste is 0.15mm thick and 0.35mm in diameter. PBGA stands for Plastic Ball Grid Array. The terminal A1 corner must be on the top surface by using a corner chamfer, ink, metallized markings or some other feature of the package body or internal heatslug. A distinguishing feature is allowed on the bottom surface of the package to identify terminal the A1 corner. Exact shape of each corner is optional.
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Package information - mechanical data
STE12PS
Figure 17. PBGA23x23 package mechanical drawing
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Ordering information
9
Ordering information
Table 13. Order codes
Temp range, C -40 to +85 Package PBGA (23mm x 23mm x 1.82mm)
Part number E-STE12PS(1)
1. E-: ECOPACK(R)
10
Revision history
Table 14.
Date 10-Nov-2006
Document revision history
Revision 1 Initial release Changes
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